1. Field of the Invention
The present invention relates to a fabrication method of a transistor, and more particularly to a fabrication method of a low-temperature polysilicon thin film transistor (LTPS-TFT).
2. Description of the Related Art
Generally, devices use switches to control the operation thereof. For example, active matrix displays use thin film transistors (TFT) as driving components. According to the material of a channel layer of the TFT, the types of the TFT include amorphous silicon TFT and polysilicon TFT. Based on the position of the channel layer corresponding to that of the gate, the types of TFT also include top-gate TFT and bottom-gate TFT. The bottom-gate TFT has an insulating/amorphous silicon layer interface which is capable of preventing contamination during process. The fabrication method can also be integrated with the back-channel etching technology. The bottom-gate TFT, therefore, is more popularly used for the switching devices of liquid crystal displays. Furthermore, compared with the amorphous silicon TFT, the polysilicon TFT has low power consumption and high electron mobility. It also gets more attention in the industry as well.
The prior art method of fabricating the polysilicon TFT requires a high temperature process up to 1000° C. Due to the high temperature requirement, the choice of the substrate material that can be applied to the process is limited. By the development of laser technology, the processing temperature can be substantially down to or under 600° C. The polysilicon TFT fabricated by such process is called a low-temperature polysilicon TFT (LTPS-TFT). The technology utilizes the laser annealing process to melt and recrystalize the amorphous silicon layer into polysilicon layer. The normally used laser annealing process is the excimer laser annealing (ELA) process.
Although the polysilicon TFT has the advantages of high carrier mobility and high driving current about 10−4 μA, it also creates high leakage current about 10−9 μA. The polysilicon TFT is easy to induce hot carrier effect at the drain region, causing device degradation. With the concern, the light doped drain (LDD) region is applied and disposed between the channel layer and the source/drain region of the transistor to reduce hot carrier effect.
FIGS. 1A-1E are cross-sectional views showing a method of fabricating a prior art LTPS-TFT. Referring to FIG. 1A, a gate 102, a gate dielectric layer 104 and an amorphous silicon layer 106 are sequentially formed on a substrate 100. An ELA process is performed to melt and recrystalize the amorphous silicon layer 106 into a polysilicon layer by the excimer laser beams 118. Referring to FIG. 1B, the polysilicon layer 106a is patterned to form the active region of the thin film transistor.
Referring to FIG. 1C, a silicon oxide layer 108 is formed on the polysilicon layer 106a over the gate 102. The silicon oxide layer 108 serves as a mask for implantation of ions 130 to form the ohmic contact layer 110 of the transistor. The polysilicon layer 106a formed over the gate 102 is the channel layer 112.
Referring to FIG. 1D, another silicon oxide layer 108a is form on the channel layer 112. The silicon oxide layer 108a serves as another mask for lightly-doping 140 to form the LDD region between the channel layer 112 and the ohmic contact layer 110. Referring to FIG. 1E, a source/drain region 116 is formed on the ohmic contact layer 110 and the gate dielectric layer 104 to cover a portion of the silicon oxide layer 108a. Accordingly, a bottom-gate LTPS-TFT 120 is complete.
From the prior art process, at least five masks are required to fabricate the prior art LTPS-TFT 120. In addition, the LDD process is so complicated that the method of fabricating the prior art LTPS-TFT has high manufacturing cost.